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SAMSUNG S3C2440A SMD MODULE |
PXA270 V6 SMD MODULE |
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The
S3C2440A
consists of 16-/32-bit RISC (ARM920T) CPU core, separate
16KB instruction and
16KB data cache, MMU to handle virtual memory
management, NAND
flash boot loader, System Manager (chip select logic
and SDRAM
controller), LCD controller (STN & TFT), I/O ports, 4-ch Timers
with PWM, RTC, 8-ch
10-bit ADC and touch screen, 3-ch UART, 4-ch DMA,IIC-BUS interface,
IIS-BUS interface, 2-ch SPI, AC97 interface, USB host,USB device, SD host
& multimedia card interface, Camera Interface and PLL
for clock generation,
Most peripheral pins double as
GPIOs
CPU clock 300 and 400 MHz.
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PXA270
specification: -7 Stage pipeline -32 KB instruction cache-32
KB data cache -2 KB ®mini¯ data cache -Extensive data buffering
-256 Kbytes of internal SRAM for highspeed code or data
storage
preserved during low-power states -High-speed baseband
processor
, interface (Mobile Scalable Link) -AC'97 audio port -I2S
audio port
-USB Client controller -USB Host controller -USB On-The-Go
controller
-Three high-speed UARTs (two with hardware flow control)
-FIR and
SIR infrared -JTAG interface with boundary scan -Real-time
clock. -LCD Controller -Support for PCMCIA and
CompactFlash -CPU clock from 104to 624 MHz -SD Card / MMC
Controller (with SPI mode support) -Memory Stick card controller -3
SSP controllers -2 I2Ccontrollers -4 pulse-width modulators
(PWMs) -Keypad interface with both direct and matrix keys support
-Most peripheral pins double as GPIOs
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MOTHERBOARD FOR S3C2440A SMD MODULE |
MOTHERBOARD FOR PXA270 SMD MODULE |
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Info: |
Roberto Deut
roberto.deut@serp.it
Tel. +39 0125 577525 Mob. +39 348 4417443 Fax +39 0125 577227
Assistenza tecnica
Write to the technical support
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